1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of manufacturing a semiconductor device which includes bipolar transistors and field-effect transistors formed on a semiconductor substrate.
2. Description of the Background Art
Such a BiCMOS element has been known that includes a bipolar transistor having a high-speed performance and a good drive performance, and also includes a CMOS transistor allowing high-density integration and low power consumption.
FIGS. 93 to 106 are cross sections of structures showing a process of manufacturing a first BiCMOS element in the prior art. FIG. 106 is a cross section of a structure of the conventional first BiCMOS element which is manufactured by the manufacturing process shown in FIGS. 93 to 105. Referring first to FIG. 106, description will now be given on the sectional structure of the first BiCMOS element in the prior art.
In a bipolar transistor part (A: A1, A2) of the conventional first BiCMOS element, an N.sup.+ -type collector buried layer 2 is formed on a P-type silicon substrate 1. An N-type epitaxial layer 6 is formed on the upper surface of collector buried layer 2. For element isolation, there are formed a field oxide film 7, a P-type isolation region 11 and a P.sup.+ -type lower surface isolation region 5.
A base region which is formed of a P.sup.- -type true base region 24 and a P.sup.+ -type external base region 88 is formed at a surface portion of N-type epitaxial layer 6. An N.sup.+ -type emitter region 27 is formed at the surface of this base region. An N.sup.+ -type collector wall region 8 is formed at a position spaced from external base region 88 by field oxide film 7. Collector wall region 8 has an end in contact with N.sup.+ -type collector buried layer 2.
A P.sup.+ -type external base leader electrode 23 is formed on field oxide film 7 and the surface of external base region 88. An N.sup.+ -type emitter electrode 26a is formed inside a side wall spacer 25 of an opening E1 for an emitter, and is electrically connected to emitter region 27.
P.sup.+ -type external base leader electrode 23 and N.sup.+ -type emitter electrode 26a are electrically isolated from each other by side wall spacer 25.
A CVD oxide film 28a is formed on the upper surface of emitter electrode 26a. A CVD oxide film 22a is formed on the upper surface of external base leader electrode 23. Side wall spacer 25 is formed at side surfaces of external base leader electrode 23 and CVD oxide film 22a.
At a PMOS transistor part (B) in the CMOS transistor part, an N.sup.+ -type buried layer 3 is formed at P-type silicon substrate 1. An N-type well region 9 is formed on buried layer 3. For element isolation, field oxide film 7 is formed. A pair of P-type source/drain regions 15 spaced from each other by a channel region are formed at the surface of N-type well region 9. Source/drain regions 15 are formed of P.sup.- -type source/drain regions 15a and P.sup.+ -type source/drain regions 15b. A gate electrode 13a, which is formed of, e.g., an N.sup.+ -type polycrystalline silicon film and a tungsten silicide (WSi) film, is formed on the channel region. A side wall spacer 19 is formed at the side surface of gate electrode 13a.
At an NMOS transistor part (C), a P.sup.- -type buried layer 4 is formed at P-type silicon substrate 1. A P-type well region 10 is formed on buried layer 4. For element isolation, field oxide film 7 is formed. Similarly to the PMOS transistor part, a pair of N-type source/drain regions 17 spaced from each other by a channel region are formed at the surface of P-type well region 10. Source/drain regions 17 are formed of N.sup.- -type source/drain regions 17a and N.sup.+ -type source/drain regions 17b. Gate electrode 13a, which is formed of, e.g., an N.sup.+ -type polycrystalline silicon film and a tungsten silicide (WSi) film, is formed on the channel region. Side wall spacer 19 is formed at the side surface of gate electrode 13a.
A polycrystalline silicon resistance 30a is formed on field oxide film 7 located at a polycrystalline silicon resistance part (D) neighboring to NMOS transistor part (C). A CVD oxide film 31 is formed on polycrystalline silicon resistance 30a.
An interlayer insulating film 32 is formed over bipolar transistor part (A), CMOS transistor part (B and C) and polycrystalline silicon resistance part (D). Interlayer insulating film 32 is provided with contact holes 33 which are located above collector wall region 8, emitter electrode 26a, external base leader electrode 23, source/drain regions 15, source/drain regions 17 and polycrystalline silicon resistance 30a, respectively. Although not shown, a contact hole 33 is formed also above gate electrode 13a. These contact holes 33 are filled with metal films 34 made of tungsten, respectively. Metal interconnections 35 made of, e.g., aluminum, are formed on the upper surface of interlayer insulating film 32 and are electrically connected to metal films 34, respectively.
It has been generally known to form polycrystalline silicon resistance 30a as a resistance element in an integrated circuit using a bipolar transistor as described above. FIG. 107 shows an inverter circuit using a resistance element in a bipolar transistor. In the inverter circuit shown in FIG. 107, a current flows between a collector and an emitter when a positive voltage is applied to an input voltage Vin, so that a voltage lowers at a resistance R, and thereby an output voltage Vout lowers. When input voltage Vin is at a low potential, no current flows between the collector and the emitter, so that lowering of the voltage does not occur at resistance R. Therefore, output voltage Vout is equal to Vcc, and a high potential is attained. As can be seen from the above, the resistance R in the element using the bipolar transistor performs a voltage conversion operation. A TTL (Transistor Transistor Logic) circuit and an ECL (Emitter Coupled Logic) circuit are examples of known logical circuits using the bipolar transistors and resistance elements. In these circuits, the bipolar transistor and the resistance element must be formed in the same step.
Referring to FIGS. 93 to 106, description will be given on a conventional process of manufacturing the first BiCMOS element.
As shown in FIG. 93, processing is performed to form N.sup.+ -type collector buried layer 2, N.sup.+ -type buried layer 3, P.sup.+ -type buried layer 4 and P.sup.+ -type lower surface isolating layer 5 at P-type silicon substrate 1. Then, N-type epitaxial layer 6 is formed on collector buried layer 2. Thereafter, field oxide film 7 is formed at predetermined regions of the main surface of P-type silicon substrate 1, and then N.sup.+ -type collector wall region 8, N-type well region 9, P-type well region 10 and P-type isolating region 11 are formed.
As shown in FIG. 94, gate oxide film 12 is formed on an active region surrounded by field oxide film 7. Then, an N-type polycrystalline silicon film 131 and a tungsten silicide film 132 each having a thickness of about 2000 .ANG. are deposited on gate oxide film 12 and field oxide film 7. After forming a photoresist pattern 14 at a predetermined region on tungsten silicide film 132, patterning is performed with a mask formed of photoresist pattern 14 to form gate electrode 13a shown in FIG. 95.
Thereafter, a photoresist pattern 16a is formed over bipolar transistor part (A) and NMOS transistor part (C). P-type impurity 111 is implanted into a surface of N-type well region 9 masked with photoresist pattern 16a and gate electrode 13a of PMOS transistor part (B). In this implantation, for example, ions of BF.sub.2.sup.+ are implanted under the conditions of 25 KeV and 7.times.10.sup.13 cm.sup.-2. Thereby, lightly doped P.sup.- -type source/drain regions 15a are formed. Thereafter, photoresist pattern 16a is removed.
As shown in FIG. 96, a photoresist pattern 18a covering bipolar transistor part (A) and PMOS transistor part (B) is formed, and then N-type impurity 222 is ion-implanted into the surface of P-type well region 10 masked with gate electrode 13a of NMOS transistor part (C) and photoresist pattern 18a. In this implantation, for example, ions of As.sup.+ are implanted under the conditions of 60 KeV and 3.times.10.sup.13 cm.sup.-2. Thereby, lightly doped N.sup.- -type source/drain regions 17a are formed. Thereafter, photoresist pattern 18a is removed.
After depositing a CVD oxide film (not shown) of about 2000 .ANG. in thickness, this CVD oxide film is dry-etched to form side wall spacer 19 at side surface of each gate electrode 13a, as shown in FIG. 97.
Thereafter, as shown in FIG. 98, processing is performed to form a photoresist pattern 20a covering bipolar transistor part (A) and NMOS transistor part (C). P-type impurity 333 is implanted into the surface of N-type well region 9 masked with photoresist pattern 20a, gate electrode 13a located at PMOS transistor part (B) and side wall spacer 19. Thereby, heavily doped P.sup.+ -type source/drain regions 15b are formed. In this implantation, for example, ions of BF.sub.2 are implanted under the conditions of 20 KeV and 4.times.10.sup.15 cm.sup.-2. Thereafter, photoresist pattern 20a is removed.
As shown in FIG. 99, processing is performed to form a photoresist pattern 21a covering bipolar transistor part (A) and PMOS transistor part (B). N-type impurity 444 is implanted into the surface of P-type well region 10 masked with photoresist pattern 21a, gate electrode 13a located at NMOS transistor part (C) and side wall spacer 19. In this implantation, for example, ions of As.sup.+ are implanted under the conditions of 50 KeV and 4.times.10.sup.15 cm.sup.-1. Thereby, heavily doped N.sup.+ -source/drain regions 17b are formed. Thereafter, photoresist pattern 21a is removed.
After depositing a polycrystalline silicon film (not shown) of about 2000 .ANG. in thickness on the whole surface, P-type impurity is implanted into this polycrystalline silicon film. In this implantation, for example, ions of BF.sub.2.sup.+ are implanted under the conditions of 40 KeV and 4.times.10.sup.15 cm.sup.-2. Further, a CVD oxide film (not shown) of about 2000 .ANG. in thickness is deposited on the whole surface, and then dry etching is performed with a mask formed of a photoresist pattern (not shown). Thereby, external base leader electrode 23 and CVD oxide film 22a having configurations shown in FIG. 100 are formed. Then, implantation of P-type impurity is performed for forming the true base region. In this implantation, for example, ions of BF.sub.2.sup.+ are implanted under the conditions of 20 KeV and 8.times.10.sup.13 cm.sup.-2. The step for this ion implantation is not shown. Thereafter, a CVD oxide film (not shown) of about 2000 .ANG. in thickness is deposited on the whole surface, and then this CVD oxide film is dry-etched to form side wall spacers 25 at the side surfaces of external base leader electrodes 23 and CVD oxide films 22a as shown in FIG. 101.
Then, as shown in FIG. 102, a polycrystalline silicon film 260a of about 2000 .ANG. in thickness is deposited on the whole surface, and thereafter N-type impurity 555 is ion-implanted into polycrystalline silicon film 260a. In this ion implantation, for example, ions of As.sup.+ are implanted under the conditions of 50 KeV and 1.times.10.sup.16 cm.sup.-2. Thereafter, heat treatment is performed at 850.degree. C. for about 30 minutes, so that emitter region 27 is formed. Also, true base region 24 and external base region 88 are formed. Thereafter, a CVD oxide film (not shown) of about 2000 .ANG. in thickness is deposited on the whole surface of polycrystalline silicon film 260a, and then a photoresist pattern 29 shown in FIG. 103 is formed. Dry etching is performed with a mask formed of photoresist pattern 29, so that emitter electrode 26a and overlying CVD oxide film 28a are formed as shown in FIG. 103. Thereafter, photoresist pattern 29 is removed.
Subsequently, a polycrystalline silicon film 30 of about 2000 .ANG. in thickness is deposited on the whole surface for forming a resistance element. P-type or N-type impurity 666 is ion-implanted into polycrystalline silicon film 30 with an implantation dose, an implantation energy and a kind of impurity controlled or selected to attains an intended resistance value. Then, a CVD oxide film (not shown) of about 2000 .ANG. in thickness is deposited on the whole surface, and thereafter a photoresist pattern (not shown) is formed at a predetermined region on this CVD oxide film. Using this photoresist pattern as a mask, dry etching is effected on the underlying CVD oxide film and polycrystalline silicon film 30, so that polycrystalline silicon resistance 30a and CVD oxide film 31 are formed as shown in FIG. 105.
Thereafter, interlayer insulating film 32 covering the whole surface is formed as shown in FIG. 106. Processing is performed to form contact holes 33 at regions of interlayer insulating film 32 located above collector wall region 8, emitter electrode 26a, external base leader electrode 23, source/drain regions 15, source/drain regions 17 and polycrystalline silicon resistance 30a. After filling each contact hole 33 with metal film 34 made of, e.g., tungsten, metal interconnection 35 made of, e.g., aluminum is formed on the upper surface of each metal film 34. Thereby, the conventional first BiCMOS element shown in FIG. 106 is completed.
FIGS. 108 to 111 are cross sections showing a process of manufacturing a second BiCMOS element in the prior art. Referring to FIG. 111, this conventional second BiCMOS element has the substantially same structure as the conventional first BiCMOS element shown in FIG. 106. However, this second BiCMOS element has metal silicide films 39 which are formed on the surfaces of emitter electrode 26a, external base leader electrode 23, collector wall region 8, source/drain regions 15 and 17, gate electrode 13b and polycrystalline silicon resistance 30a. Metal silicide films 39 are formed for reducing resistances of the respective electrodes and regions.
Referring to FIGS. 108 to 111, a process of manufacturing the conventional second BiCMOS element will be described below.
After the same process as that for manufacturing the conventional first BiCMOS element shown in FIG. 93, gate oxide film 12 is formed on the active region surrounded by field oxide film 7. An N-type polycrystalline silicon film 133 of about 2000 .ANG. in thickness is formed on field oxide film 7 and gate oxide film 12, and then a CVD oxide film 36 of about 2000 .ANG. in thickness is deposited on polycrystalline silicon film 133. A photoresist pattern 37 is formed at a predetermined region on CVD oxide film 36, and then patterning is performed with a mask formed of photoresist pattern 37. Thereby, gate electrodes 13b shown in FIG. 109 are formed.
Thereafter, a manufacturing process is performed similarly to that for the conventional first BiCMOS element shown in FIGS. 95 to 103. Thereby, the structure shown in FIG. 109 is obtained. Using photoresist pattern 38 as a mask for leaving portions which are not to be silicided, patterning is effected on CVD oxide films 22a, 28a, 31 and 36. Thereby, a structure shown in FIG. 110 is formed. Thereafter, photoresist pattern 38 is removed. After sputtering cobalt to the whole surface, lamp annealing is performed several times. Thereafter, cobalt is removed, so that a metal silicide film is formed on silicon and polycrystalline silicon in a self-aligned manner. This process is called a SALICIDE (Self-Aligned-Silicide) process.
The SALICIDE process is performed to form, for example, cobalt silicide films 39 on the upper surfaces of emitter electrode 26a, external base leader electrode 23, collector wall region 8, source/drain regions 15 and 17 and gate electrode 13b as well as on the contact region of polycrystalline silicon resistance 30a. Thereafter, a manufacturing process is performed similarly to that for the conventional first BiCMOS element shown in FIG. 106, so that the conventional second BiCMOS element is completed.
In the method of manufacturing the conventional first BiCMOS element shown in FIGS. 93 to 106, bipolar transistor part (A1 and A2) is subjected one time to the oxide film dry etching (DE1 in FIG. 97) during formation of the CMOS transistor part (B and C). Meanwhile, the CMOS transistor part (B and C) is subjected one time to the oxide film dry etching (DE2 in FIG. 101) during formation of bipolar transistor part (A1 and A2), and is also unavoidably subjected three times to the polycrystalline silicon dry etching (DE3 in FIG. 100, DE4 in FIG. 103 and DE5 in FIG. 105). Particularly, in the step of effecting the polycrystalline silicon dry etching on the polycrystalline silicon films on source/drain regions 15 and 17, such a disadvantage arises that source/drain regions 15 and 17 at the surface of silicon substrate 1 are etched to a large extent, because the polycrystalline silicon film and underlying silicon substrate 1 are present continuously to each other and a select ratio of etching is not substantially present between the polycrystalline silicon film and silicon substrate 1. In this case, irregularities, i.e., concave and convex portions are formed at the surface regions of source/drain regions 15 and 17, and therefore the regions doped with impurity partially decreases, which results in disadvantageous variations in junction leak and transistor characteristics as well as unacceptable characteristics.
At the active region (A1) of the bipolar transistor, the emitter/base junction is exposed on the surface. Therefore, a base leak current occurs when the surface of active region of the bipolar transistor is subjected to the dry etching.
Since the polycrystalline silicon resistance is formed of the polycrystalline silicon film which is dedicated to formation of the resistance, this increases the steps in number.
The manufacturing process for the conventional second BiCMOS element shown in FIGS. 108 to 111 employs the step of effecting the oxide film dry etching (DE6) on the surfaces of source/drain regions 15 and 17 in addition to the steps in the manufacturing process for the conventional first BiCMOS element described above. Due to the fact that the dry etching is performed many times, field oxide film 7 is also subjected to the etching, so that the film thickness of the field oxide film 7 is disadvantageously reduced. In the worst case, as shown in FIG. 112, field oxide film 7 disappears, so that source/drain regions 15 of the PMOS transistor are connected to source/drain regions 17 of the NMOS transistor via silicide film 39, resulting in short-circuit. In some cases, source/drain regions 15 of the PMOS transistor are connected to P-type isolating region 11, P-type lower surface isolating region 5 and P-type silicon substrate 1, resulting in short-circuit. In these cases, an operation failure may occur in the transistor.
In order to prevent the above disadvantages, the dry etching may be performed with a photoresist pattern or the like masking regions not to be dry-etched. However, this remarkably increases the steps in number, and therefore complicates the manufacturing process.
As described above, it is impossible in the prior art to reduce an etching damage to the bipolar transistor part and CMOS transistor part while simplifying a manufacturing process.